Datasheet Summary
CMOS SyncFIFO 64 x 36
Integrated Device Technology, Inc.
Features
:
- Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge)
- 64 x 36 storage capacity
- Synchronous data buffering from Port A to Port B
- Mailbox bypass register in each direction
- Programmable Almost-Full (AF) and Almost-Empty (AE) flags
- Microprocessor Interface Control Logic
- Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
- Empty Flag (EF) and Almost-Empty (AE) flags synchronized by CLKB
- Passive parity checking on each Port
- Parity Generation can be selected for each Port
- Supports clock frequencies up to...