IDT723613 Datasheet | Integrated Device Technology

CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36 Integrated Device Technology, Inc. Features : - Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) - 64 x 36 storage capacity FIFO buffering data from Port A to Port B - Mailbox bypass registers in each direction - Dynamic Port B bus sizing of 36-bits (long word), 18-bits (word), and 9-bits (byte) - Selection of Big- or Little-Endian format for word and byte bus sizes - Three modes of byte-order swapping on Port B - Programmable Almost-Full and Almost-Empty flags - Microprocessor interface control logic - FF, AF flags synchronized by...