QS5LV919160J Description
QS5LV919 3.3V operation JEDEC patible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0 Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable.
| Part Number | Description |
|---|---|
| QS5LV919160Q | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER |
| QS5LV919133Q | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER |
| QS5LV91955J | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER |
| QS5LV91955Q | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER |
| QS5LV91970J | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER |
QS5LV919 3.3V operation JEDEC patible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0 Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable.