QS5LV91970J Datasheet | Integrated Device Technology

QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER Features : DESCRIPTION: QS5LV919 - - - - - - - - - - - - - 3.3V operation JEDEC patible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0- Q4 2x Q output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to MC88LV915, IDT74FCT388915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24m A 160MHz maximum frequency (2x Q output) Available in QSOP and PLCC packages The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2x Q, Q 0-Q 4, Q5, Q/2. Careful layout and design ensure < 300 ps skew between the Q 0-Q 4, and Q/2 outputs. The QS5LV919 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external ponents. Various binations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5LV919 is designed for use in high-performance workstations, multiboard puters, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM REF_SEL LO CK SYNC 0 SYNC 1 O E/RST 0 0 1 PH A SE DETECTO R LOO P FILTER 1 FEEDBACK PLL_EN FREQ...