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IS45S32800D - 8M x 32 256Mb SYNCHRONOUS DRAM

This page provides the datasheet information for the IS45S32800D, a member of the IS42S32800D 8M x 32 256Mb SYNCHRONOUS DRAM family.

Description

A0-A11 A0-A8 BA0, BA1 DQ0 to DQ31 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM0-DQM3 Vdd Vss Vddq Vssq NC Wri

Features

  • Clock frequency: 166, 143 MHz.
  • Fully synchronous; all signals referenced to a positive clock edge.
  • Internal bank for hiding row access/precharge.
  • Single Power supply: 3.3V + 0.3V.
  • LVTTL interface.
  • Programmable burst length.
  • (1, 2, 4, 8, full page).
  • Programmable burst sequence: Sequential/Interleave.
  • Auto Refresh (CBR).
  • Self Refresh.
  • 4096 refresh cycles every 16ms (A2 grade) or 64 ms (Com.

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Datasheet Details

Part number IS45S32800D
Manufacturer Integrated Silicon Solution
File Size 899.91 KB
Description 8M x 32 256Mb SYNCHRONOUS DRAM
Datasheet download datasheet IS45S32800D Datasheet
Additional preview pages of the IS45S32800D datasheet.

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IS42S32800D IS45S32800D www.DataSheet4U.com 8M x 32 256Mb SYNCHRONOUS DRAM APRIL 2009 FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.
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