IS45S32800D Datasheet | ISSI

FEATURES - Clock frequency: 166, 143 MHz - Fully synchronous; all signals referenced to a positive clock edge - Internal bank for hiding row access/precharge - Single Power supply: 3.3V + 0.3V - LVTTL interface - Programmable burst length - (1, 2, 4, 8, full page) - Programmable burst sequence: Sequential/Interleave - Auto Refresh (CBR) - Self Refresh - 4096 refresh cycles every 16ms (A2 grade) or 64 ms (mercial, Industrial, A1 grade) - Random column address every clock cycle - Programmable CAS latency (2, 3 clocks) - Burst read/write and burst read/single write operations capability - Burst termination by burst stop and precharge mand OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized in 2Meg x 32 bit x 4 Banks. KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 6 10 166 100 5.4 6.5 -7 7 10 143 100 5.4 6.5 -75E Unit - ns 7.5 ns - Mhz 133 Mhz - ns 5.5 ns ADDRESS TABLE Parameter Configuration Refresh Count ./Ind. A1 A2 Row Addresses Column Addresses Bank Address Pins Autoprecharge Pins 8M x 32 2M x 32 x 4 banks 4K / 64ms 4K / 64ms 4K / 16ms A0 - A11 A0 - A8 BA0, BA1 A10/AP OPTIONS - Package: 86-pin TSOP-II 90-ball TF-BGA - Operating Temperature Range: mercial (0o C to +70o C) Industrial (-40o C to +85o C) Automotive Grade, A1 (-40o C to +85o C) Automotive Grade, A2 (-40o C to +105o C) - Die Revision: D Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein....