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IS49NLS18160 - Separate I/O RLDRAM 2 Memory

Download the IS49NLS18160 datasheet PDF. This datasheet also covers the IS49NLS93200 variant, as both devices belong to the same separate i/o rldram 2 memory family and are provided as variant models within a single manufacturer datasheet.

General Description

1.1 288Mb (32Mx9) Separate I/O BGA Ball-out (Top View) 123 4 5678 9 10 11 12 A VREF B VDD VSS DNU3 VEXT DNU3 VSS VSSQ VSS VEXT TMS TCK VSSQ Q0 D0 VDD C VTT DNU3 DNU3 VDDQ VDDQ Q1 D1 VTT D A221 DNU3 DNU3 VSSQ VSSQ QK0# QK0 VSS E A211 DNU3 DNU3 VDDQ VDDQ Q2 D2 A20

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS49NLS93200-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS49NLC18160A Common I/O RLDRAM 2 Memory ISSI
IS49NLC36800A Common I/O RLDRAM 2 Memory ISSI
IS49NLC93200A Common I/O RLDRAM 2 Memory ISSI
IS49RL18128 4 Meg x 18 x 16 Banks x 2 Ranks RLDRAM3 ISSI
IS49RL36640 2Meg x 36 x 16 Banks RLDRAM3 ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS49NLS18320 Separate I/O RLDRAM 2 Memory
IS49NLS18320A Separate I/O RLDRAM 2 Memory
IS49NLS93200 Separate I/O RLDRAM 2 Memory
IS49NLS96400 Separate I/O RLDRAM 2 Memory
IS49NLS96400A Separate I/O RLDRAM 2 Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS49NLS93200,IS49NLS18160 288Mb (x9, x18) Separate I/O RLDRAM® 2 Memory FEATURES ADVANCED INFORMATION SEPTEMBER 2012 • 533MHz DDR operation (1.067 Gb/s/pin data rate) • 38.4 Gb/s peak bandwidth (x18 Separate I/O at 533 MHz clock frequency) • Reduced cycle time (15ns at 533MHz) • 32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms) • 8 internal banks • Non-multiplexed addresses (address multiplexing option available) • SRAM-type interface • Programmable READ latency (RL), row cycle time, and burst sequence length • Balanced READ and WRITE latencies in order to optimize data bus utilization • Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK.