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IS61DDB41M36 - DDR-II (Burst of 4) CIO Synchronous SRAMs

Download the IS61DDB41M36 datasheet PDF. This datasheet also covers the IS61DDB42M18 variant, as both devices belong to the same ddr-ii (burst of 4) cio synchronous srams family and are provided as variant models within a single manufacturer datasheet.

General Description

The 36Mb IS61DDB41M36 and IS61DDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 1M x 36 or 2M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with late write operation.
  • Double data rate (DDR-II) interface for read and write input ports.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges only.
  • Two input clocks (C an.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDB42M18-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for IS61DDB41M36 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IS61DDB41M36. For precise diagrams, and layout, please refer to the original PDF.

36 Mb (1M x 36. & 2M x 18) ISSIDDR-II (Burst of 4) CIO Synchronous SRAMs ® Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • ...

View more extracted text
x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation. • Double data rate (DDR-II) interface for read and write input ports. • Fixed 4-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two input clocks (C and C) for data output control. May 2005 • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.

More Datasheets from ISSI (now Infineon)

Part Number Description
IS61DDB41M36A 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M18A 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB42M18 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M18A 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB42M36 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M36A 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB44M18 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB44M18A 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB451236A 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB21M18A 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM