IS61DDB41M36 Overview
The 36Mb IS61DDB41M36 and IS61DDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a mon I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
IS61DDB41M36 Key Features
- 1M x 36 or 2M x 18
- On-chip delay-locked loop (DLL) for wide data valid window
- mon I/O read and write ports
- Synchronous pipeline read with late write operation
- Double data rate (DDR-II) interface for read and write input ports
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K) for address and control registering at rising edges only
- Two input clocks (C and C) for data output control
- Two echo clocks (CQ and CQ) that are delivered simultaneously with data