IS61DDB451236A Description
512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid window. mon I/O read and write ports.
IS61DDB451236A Key Features
- 512Kx36 and 1Mx18 configuration available
- On-chip delay-locked loop (DLL) for wide data valid window
- mon I/O read and write ports
- Synchronous pipeline read with late write operation
- Double Data Rate (DDR) interface for read and write input ports
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control registering at rising edges only
- Two input clocks (C and C#) for data output control
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data