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IS61VPS102418B - SINGLE CYCLE DESELECT STATIC RAM

Download the IS61VPS102418B datasheet PDF. This datasheet also covers the IS61LPS51236B variant, as both devices belong to the same single cycle deselect static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

The 18Mb product family

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and.
  • control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Single cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JEDEC 100-pin.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61LPS51236B-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61VPS102436B 36Mb Single CYCLE DESELECT STATIC RAM ISSI
IS61VPS12832EC SINGLE CYCLE DESELECT SRAM ISSI
IS61VPS12836EC SINGLE CYCLE DESELECT SRAM ISSI
IS61VPS204818B 36Mb Single CYCLE DESELECT STATIC RAM ISSI
IS61VPS25618EC SINGLE CYCLE DESELECT SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61VPS102418A 18Mb Single CYCLE DESELECT STATIC RAM
IS61VPS102436A 36Mb Single CYCLE DESELECT STATIC RAM
IS61VPS12836A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM
IS61VPS204818A 36Mb Single CYCLE DESELECT STATIC RAM
IS61VPS25618A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B 512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM AUGUST 2017 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages • Power supply: LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) VPS: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) VVPS: VDD 1.8V (± 5%), VDDQ 1.