80960MC Datasheet | Intel Corporation

PRELIMINARY EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT mercial s High-Performance Embedded Architecture s On-Chip Memory Management Unit - 25 MIPS Burst Execution at 25 MHz - 9.4 MIPS- Sustained Execution at 25 MHz s On-Chip Floating Point Unit - Supports IEEE 754 Floating Point Standard - Full Transcendental Support - Four 80-Bit Registers - 13.6 Million Whetstones/s (Single Precision) at 25 MHz s 512-Byte On-Chip Instruction Cache - Direct Mapped - Parallel Load/Decode for Uncached Instructions s Multiple Register Sets - Sixteen Global 32-Bit Registers - Sixteen Local 32-Bit Registers - Four Local Register Sets Stored...