Datasheet Summary
April 1995
Radiation Hardened Triple Three-Input NAND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C TOP VIEW
A1 1 B1 2 A2 3 B2 4 14 VCC 13 C1 12 Y1 11 C3 10 B3 9 A3 8 Y3
Features
- 1.25 Micron Radiation Hardened SOS CMOS
- Total Dose 300K RAD (Si)
- Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ)
- SEU LET Threshold >80
- Dose Rate Upset >1011 MEV-cm2 /mg
RAD (Si)/s, 20ns Pulse -55oC +125oC
- Latch-Up Free Under Any Conditions
- Military Temperature Range: to
C2 5 Y2 6 GND 7
- Significant Power Reduction pared to ALSTTL Logic
- DC Operating Voltage Range: 4.5V to 5.5V
- Input Logic Levels
- VIL = 30% of VCC Max...
