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CD4015BT - CMOS Dual 4-Stage Static Shift Register

General Description

only.

Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.

Accordingly, the reader is cautioned to verify that data sheets are current before placing orders.

Key Features

  • QML Class T, Per MIL-PRF-38535.
  • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - SEP Effective LET > 75 MEV/gm/cm2.
  • Medium Speed Operation 12MHz (typ. ) Clock Rate at VDD - VSS = 10V.
  • Fully Static Operation.
  • 8 Master-Slave Flip-Flops Plus Input and Output Buffering.
  • 100% Tested For Quiescent Current at 20V.
  • 5V, 10V and 15V Parametric Ratings.
  • Standardized Symmetrical Output Characteristics Pinouts CD4015BT (SBDIP),.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD4015BT Data Sheet July 1999 File Number 4621.1 CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. CD4015BT consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages are D type, master-slave flip-flops.