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HMA5101 - 16 x 16-Bit CMOS Parallel Multiplier Accumulator

General Description

The HMA510/883 is a high speed, low power CMOS 16 x 16-bit parallel multiplier accumulator capable of operating at 55ns clocked multiply-accumulate cycles.

The 16-bit X and Y operands may be specified as either two’s complement or unsigned magnitude format.

Key Features

  • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
  • 16 x 16-Bit Parallel Multiplication with Accumulation to a 35-Bit Result.
  • High-Speed (55ns) Multiply Accumulate Time.
  • Low Power CMOS Operation - ICCSB = 500µA Maximum - ICCOP = 7.0mA Maximum at 1.0MHz.
  • HMA510/883 is Compatible with the CY7C510 and the IDT7210.
  • Supports Two’s Complement or Unsigned Magnitude Operations.

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Full PDF Text Transcription for HMA5101 (Reference)

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HMA510/883 April 1997 16 x 16-Bit CMOS Parallel Multiplier Accumulator Description The HMA510/883 is a high speed, low power CMOS 16 x 16-bit parallel multiplier accumula...

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a high speed, low power CMOS 16 x 16-bit parallel multiplier accumulator capable of operating at 55ns clocked multiply-accumulate cycles. The 16-bit X and Y operands may be specified as either two’s complement or unsigned magnitude format. Additional inputs are provided for the accumulator functions which include: loading the accumulator with the current product, adding or subtracting the accumulator contents and the current product, and preloading the Accumulator Registers from the external inputs. All inputs and outputs are registered. The registers are all positive edge triggered, and are latched on the rising edge of t

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