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HSP50306 Datasheet Digital QPSK Demodulator

Manufacturer: Intersil (now Renesas)

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General Description

The HSP50306 is a 6-bit QPSK demodulator chip designed for use in high signal to noise environments which have some multipath distortion.

The part recovers 2.048 MBPS data from samples of a QPSK modulated 10.7MHz or 2.1MHz carrier.

The chip coherently demodulates the waveform, recovers symbol timing, adaptively equalizes the signal to remove multipath distortion, differentially decodes and multiplexes the data decisions.

Overview

HSP50306 February 1998 Digital QPSK Demodulator.

Key Features

  • 25.6MHz or 26.97MHz Clock Rates.
  • Single Chip QPSK Demodulator with 10kHz Tracking Loop.
  • Square Root of Raised Cosine (α = 0.4) Matched Filtering.
  • 2.048 MBPS Reconstructed Output Data Stream.
  • Bit Synchronization with 3kHz Loop Bandwidth.
  • Internal Equalization for Multipath Distortion.
  • 6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF.
  • Level Detection for External IF AGC Loop.
  • 0.1s Acquisition Time.
  • 10-9 BER.

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