HSP50306 Datasheet PDF - Intersil Corporation Digital QPSK Demodulator Specs

HSP50306 - Digital QPSK Demodulator

Datasheet Summary

Description

The HSP50306 is a 6-bit QPSK demodulator chip designed for use in high signal to noise environments which have some multipath distortion.

The part recovers 2.048 MBPS data from samples of a QPSK modulated 10.7MHz or 2.1MHz carrier.

Features

25.6MHz or 26.97MHz Clock Rates.
Single Chip QPSK Demodulator with 10kHz Tracking Loop.
Square Root of Raised Cosine (α = 0.4) Matched Filtering.
2.048 MBPS Reconstructed Output Data Stream.
Bit Synchronization with 3kHz Loop Bandwidth.
Internal Equalization for Multipath Distortion.
6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF.
Level Detection for External IF AGC Loop.
0.1s Acquisition Time.
10-9 BER.

Datasheet Details

Part number	HSP50306
Manufacturer	Intersil Corporation
File Size	37.78 KB
Description	Digital QPSK Demodulator
Datasheet	HSP50306 Datasheet
Additional preview pages of the HSP50306 datasheet.

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Full PDF Text Transcription

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HSP50306 February 1998 Digital QPSK Demodulator Description The HSP50306 is a 6-bit QPSK demodulator chip designed for use in high signal to noise environments which have some multipath distortion. The part recovers 2.048 MBPS data from samples of a QPSK modulated 10.7MHz or 2.1MHz carrier. The chip coherently demodulates the waveform, recovers symbol timing, adaptively equalizes the signal to remove multipath distortion, differentially decodes and multiplexes the data decisions. 8-A lock signal is provided to indicate when the tracking loops are locked and the data decisions are valid. To optimize performance, a gain error feedback signal is provided which can be ﬁltered and used to close an I.F. AGC loop around the A/D converter. The QPSK demodulator derives all timing from CLKIN.

Published: Mar 26, 2005 |