HUF75639S3S Datasheet | Intersil

Features - 56A, 100V - Simulation Models - Temperature pensated PSPICETM and SABER© Electrical Models - Spice and Saber Thermal Impedance Models - .Intersil. - Peak Current vs Pulse Width Curve - UIS Rating Curve - Related Literature - TB334, “Guidelines for Soldering Surface Mount ponents to PC Boards” Symbol Ordering Information PART NUMBER HUF75639G3 HUF75639P3 HUF75639S3S PACKAGE TO-247 TO-220AB TO-263AB BRAND 75639G 75639P 75639S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75639S3ST. Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (FLANGE) JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (TAB) JEDEC TO-263AB DRAIN (FLANGE) GATE SOURCE CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. Ultra FET™ is a trademark of Intersil Corporation. PSPICE™ is a trademark of Micro Sim Corporation. SABER© is a Copyright of Analogy Inc. http://.intersil. or 407-727-9207 | Copyright © Intersil Corporation 1999 HUF75639G3, HUF75639P3, HUF75639S3S Absolute Maximum Ratings TC = 25o C, Unless Otherwise Specified 100 100 ±20 56 Figure 4 Figures 6, 14, 15 200 1.35 -55 to 175 300 260 UNITS V V V A Drain to Source Voltage (Note 1) - - - - - - - - . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) - - - - - - . . VDGR Gate to Source Voltage - - -...