KK4019B
KK4019B is Quad AND/OR Select Gate High-Voltage Silicon-Gate CMOS manufactured by Kodenshi AUK Group.
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TECHNICAL DATA
Quad AND/OR Select Gate
High-Voltage Silicon-Gate CMOS
The KK4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input gate. Selection is acplished by control bits Sa and Sb .In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to acplish the logical A + B function
- Operating Voltage Range: 3.0 to 18 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 n A at 18 V and 25°C
- Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
ORDERING INFORMATION KK4019BN Plastic KK4019BDW SOIC TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Sa H H L L L H H PIN 16 =VCC PIN 8 = GND H H Sb L L H H L H H H H A H L X X X L L H H B X X H L X L H L H Outputs Y H L H L L L H H H
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MAXIMUM RATINGS-
Symbol VCC VIN VOUT IIN PD PD Tstg TL
- Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±10 750 500 100 -65 to +150 260
Unit V V V m A m W m W °C °C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Remended Operating Conditions. +Derating
- Plastic DIP:
- 10 m W/°C from 65° to 125°C SOIC Package: :
- 7 m W/°C from 65° to 125°C
REMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature,...
