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ML145106 - PLL Frequency Synthesizer CMOS

Datasheet Summary

Description

P0 P8 Programmable Inputs (PDIP Pins 17 9; SOG Pins 19, 17 14, 12

9) Programmable divider inputs (binary).

Pin 2) Frequency input to programmable divider (derived fromVCO).

Features

  • res 4 and 5 are examples of some possibilities. In the aircraft synthesizer of Figure 5, the VHF loop (top) will provide a 50 kHz, 360 channel system with 10.7 MHz R/T offset when only the 11.0500 MHz (transmit) and 12.1200 MHz (receive) frequencies are provided to mixer #1. When these signals are provided with crystal oscillators, the result is a three crystal 360 channel, 50 kHz step synthesizer. When using the offset loop (bottom) in Figure 5 to provide the indicated injection frequencies fo.

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Datasheet Details

Part number ML145106
Manufacturer LANSDALE Semiconductor
File Size 266.14 KB
Description PLL Frequency Synthesizer CMOS
Datasheet download datasheet ML145106 Datasheet
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Full PDF Text Transcription

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www.DataSheet4U.com ML145106 PLL Frequency Synthesizer CMOS INTERFACES WITH DUAL–MODULUS PRESCALERS Legacy Device: Motorola MC145106 The ML145106 is a phase–locked loop (PLL) frequency synthesizer constructed in CMOS on a single monolithic structure. This synthesizer finds applications in such areas as AM radio, shortwave, amateur radio, CB and FM transceivers. The device contains an oscillator/amplifier, a 210 or 211 divider chain for the oscillator signal, a programmable divider chain for the input signal, and a phase detector. The ML145106 has circuitry for a 10.24 MHz oscillator or may operate with an external signal. The circuit provides a 5.12 MHz output signal, which can be used for frequency tripling.
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