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MD56V62160E - SYNCHRONOUS DYNAMIC RAM

Datasheet Summary

Description

The MD56V62160E is a 4-Bank  1,048,576-word  16-bit Synchronous dynamic RAM fabricated in LAPIS Semiconductor’s silicon-gate CMOS technology.

The device operates at 3.3 V.

The inputs and outputs are LVTTL compatible.

Features

  • Silicon gate, quadruple poly-silicon CMOS, 1-transistor memory cell.
  • 4-Bank  1,048,576-word  16-bit configuration.
  • Single 3.3 V power supply, 0.3 V tolerances.
  • Input : LVTTL compatible.
  • Output : LVTTL compatible.
  • Refresh : 4096 cycles/64 ms.
  • Programmable data transfer mode - CAS Latency (2, 3) - Burst Length (1, 2, 4, 8, Full Page) - Data scramble (sequential, interleave).
  • CBR auto-refresh, Self-refresh capability.

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Datasheet Details

Part number MD56V62160E
Manufacturer LAPIS
File Size 422.68 KB
Description SYNCHRONOUS DYNAMIC RAM
Datasheet download datasheet MD56V62160E Datasheet
Additional preview pages of the MD56V62160E datasheet.

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Full PDF Text Transcription

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MD56V62160E 4-Bank  1,048,576-Word  16-Bit SYNCHRONOUS DYNAMIC RAM FEDD56V62160E-07 Issue Date: Nov. 18, 2013 DESCRIPTION The MD56V62160E is a 4-Bank  1,048,576-word  16-bit Synchronous dynamic RAM fabricated in LAPIS Semiconductor’s silicon-gate CMOS technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES • Silicon gate, quadruple poly-silicon CMOS, 1-transistor memory cell • 4-Bank  1,048,576-word  16-bit configuration • Single 3.3 V power supply, 0.
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