L29C525JC15 Datasheet | LOGIC Devices Incorporated

L29C525 DEVICES INCORPORATED Dual Pipeline Register L29C525 DEVICES INCORPORATED Dual Pipeline Register DESCRIPTION The L29C525 is a high-speed, low power CMOS pipeline register. It is pin-for-pin patible with the AMD Am29525. The L29C525 can be configured as two independent 8-level pipelines or as a single 16-level pipeline. The configuration implemented is determined by the instruction code (I1-0) as shown in Table 2. The I1-0 instruction code controls the internal routing of data and loading of each register. For instruction I1-0 = 00 (Push A and B), data applied at the D 7-0 inputs is latched into register A0 on the rising edge of CLK. The contents of A0 simultaneously move to...