ISPPAC20 - In-System Programmable Analog Circuit

Description

Functional Block Diagram VCC MSEL GND OUT1 OUT2 IA IN1 IA OA IN2 IA IN3 IA OA CPIN Analog Routing Pool E2CMOS Mem Reference Auto-Cal ISP Control CP Logic CP1OUT Logic Window CP CP2OUT 3VREF 1.5VREF DAC DACOUT JTAG/SPI D0D7 VREFOUT CMVIN CAL DMODE ENSPI CS PC Typical Application

Features

IN-SYSTEM.

Lattice Semiconductor

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Datasheet Details

Part number	ISPPAC20
Manufacturer	Lattice Semiconductor
File Size	515.52 KB
Description	In-System Programmable Analog Circuit
Datasheet	ISPPAC20 Datasheet
Additional preview pages of the ISPPAC20 datasheet.

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Full PDF Text Transcription

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ispPAC ®20 In-System Programmable Analog Circuit Features • IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG — Two Instrument Amplifier Gain/Attenuation Stages — Signal Summation (Up to 3 Inputs) — Precision Active Filtering (10kHz to 100kHz) — 8-Bit DAC and Fast Dual Comparator — Non-Volatile E2CMOS® Cells (10,000 Cycles) — IEEE 1149.1 JTAG Serial Port Programming • LINEAR ELEMENT BUILDING BLOCKS — Programmable Gain Range (0dB to 40dB) — Bandwidth of 550kHz (G=1), 330kHz (G=10) — Low Distortion (THD < -74dB max @ 10kHz) — Auto-Calibrated Input Offset Voltage • TRUE DIFFERENTIAL I/O — High CMR (69dB) Instrument Amplifier Inputs — 2.

Published: Jul 20, 2006 |