ISPPAC30 Overview
The ispPAC®30 is a member of the Lattice family of InSystem Programmable (ISP™) analog integrated circuits. It is digitally configured via SRAM and utilizes E2CMOS memory for non-volatile storage of its configuration. The flexibility of ISP enables programming, verification and unlimited reconfiguration, directly on the printed circuit board.
ISPPAC30 Key Features
- Flexible Interface and Programming Control
- Full configuration capability, SPI or JTAG modes Unlimited device updates using SRAM register E2CMOS® for non-volatile co
- Four Input Instrumentation Amplifiers (IA’s)
- Two Configurable Rail-to-Rail Output Amps
- Single-ended, 0V to 5V output swing Gain bandwidth product >15MHz Amplifier, filter, integrator or parator modes 7 filter f
- Two 4-Quadrant, 8-Bit Multiplying DACs
- Full bandwidth when used as a multiplier IN3- Precision gain (<0.01 steps) with signal as input
- Precision offset (in 7 ranges) using internal Vref IN4+
- Routing of all I/O to any IA or MDAC Any IA/MDAC summed to either output amplifier Circuits with and without feedback pos
- Analog Input/Summation Routing Pools