MX98725 Datasheet | Macronix

FEATURES - - - - - - - - - - A single chip solution integrates 100/10 Base-T fast Ethernet MAC, PHY and PMD Fully ply to IEEE 802.3u specification Operates over 100 meters of STP and category 5 UTP cable Support full and half duplex operation in both 100 Base-TX and 10 Base-T mode Fully ply to PCI spec. 2.1 with bus clock ranges from 16MHz to 33MHz Fully ply to Advanced Configuration and Power Interface (ACPI) Rev 1.0 Fully ply to PCI Bus Power Management Interface spec. Rev 1.0 Magic Packet TM mode to support Remote-Power On and Remote-Wake-Up. 100/10 Base-T NWAY auto negotiation function Large on chip FIFOs for both transmit and receive operations without external local memory - - - Bus master architecture with linked host buffers delivers the most optimized performance 32-bit bus master DMA channel provides ultra low CPU utilization Proprietary Adaptive Network Throughput Control (ANTC) technology to optimize data integrity and throughput Support up to 256K bytes boot ROM and FLASH interface Three levels of loopback diagnostic capability Support a variety of flexible address filtering modes with 16 CAM address and 512 bits hash Micro Wire interface to EEPROM for customer's IDs and configuration data Single +5.0V power supply, standard CMOS technology, 160 pin PQFP package - - - - - ( Magic Packet technology is a trademark of Advanced Micro Device Corp.) 2. GENERAL DESCRIPTIONS The MX98725, second generation of 100/10 Base-T single chip MAC controller, is designed specifically to meet future demand on Fast Ethernet networking system. Different from MX98715/715a3, MX98725 additionally supports ACPI, Remote-Wake-Up, Remote-Power On, and up to 256K Bytes Flash interface to enhance product's added-on value. The MX9725 controller is an IEEE802.3u pliant single chip 32-bit full duplex, 10/100Mbps highly integrated Fast Ethernet bo solution, designed to address high performance local area networking (LAN) system application requirements. The bus master architecture...