MX98728EC Overview
MX98728EC GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION 1.6KB TX FIFO to support maximum network throughput in the full duplex mode 16/8 bits SRAM interface of the packet buffer supporting burst DMA for on-chip FIFOs Flexible packet buffer partition and addressing space for up to 1MB NWAY autonegotiation function to automatically set up network speed and protocol 3 loop back modes for...
MX98728EC Key Features
- 32 bits general purpose asynchronous bus architecture up to 33Mhz for easy system application
- Single chip solution integrating 10/100 TP transceiver to reduce overall cost
- Optional MII interface for external tranceiver
- Fully pliant with the IEEE 802.3u spec
- Supports 32/16 bits x1, x2, x4 burst read transfers for the receive packet buffer
- Packet buffer access through an IO mapped port or host DMA for a wide variety of bus