MX98728EC Datasheet | Macronix

Features - 32 bits general purpose asynchronous bus architecture up to 33Mhz for easy system application - Single chip solution integrating 10/100 TP transceiver to reduce overall cost - Optional MII interface for external tranceiver. - Fully pliant with the IEEE 802.3u spec. - Supports 32/16 bits x1, x2, x4 burst read transfers for the receive packet buffer - Packet buffer access through an IO mapped port or host DMA for a wide variety of bus applications - Programmable bus integrity check timer and interrupt assertion scheme - Supports 16/8 bits packet buffer data width and 32/ 16 bits host bus data width - Separated TX and RX FIFOs to support the full duplex mode, independent TX and RX channel - Rich on-chip registers to support a wide variety of network management functions 1.1 Introduction MX98728EC ( GMAC ) is a general purpose single chip 10/100 Fast Ethernet controller. With no glue logic or very little extra logic, it can be used in a variety of system applications through its host bus interface. Single chip solution will help reduce system cost, not only on the IC count but also on the board size. Full NWAY function with 10/100 transceiver will ease the field installation. Simply plug the chip in and it will connect itself with the best protocol available. A data cache is also used on the host bus to deliver the 32 /16 bits burst read on the host data port up to 4 data transfers in a single cycle. Two hand shake signals to municate to the host bus interface during the data port transfer are simple and fast for the system integrator. An intelligent built-in SRAM bus arbiter will manage all SRAM access requests from the host bus access, the transmit local DMA and the receive local DMA. The 16/8 bit SRAM interface with local DMAs help system developers to optimize the performance. The behavior of these local DMAs can be easily adjusted by the optional bits on the chip. (The term "packet buffer" and "packet memory" are used interchangeably in this...