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DS31406 - Single DPLL Timing IC

General Description

The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications.

On each of its two input clocks and fourteen output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz.

Key Features

  • and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator the DS31406 meets the requirements of Stratum 2, 3E, 3, 4E, and 4, G.812 Types I.
  • IV, G.813, and G.8262. Features  Two Input Clocks       Differential or CMOS/TTL Format Any Frequency from 2kHz to 750MHz Fractional Scaling for 64B/66B and FEC Scaling (e. g. , 64/66, 237/255, 238/255) or Any Other Downscaling Requirement Continuous Input Clock Quality Monitoring Automatic or Ma.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ABRIDGED DATA SHEET 19-5711; Rev 0; 12/10 DS31406 2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter General Description The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its two input clocks and fourteen output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz. The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the rest of the device.