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MAX3872 - Multirate Clock and Data Recovery

Key Features

  • o Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps, 1.244Gbps, 622.08Mbps, 155.52Mbps, 1.25Gbps/2.5Gbps (Ethernet) o Reference Clock Not Required for Data Acquisition o Exceeds ANSI, ITU, and Bellcore SONET/SDH Jitter Specifications o 2.7mUIRMS Jitter Generation o 10mVP-P Input Sensitivity Without Threshold Adjust o 0.65UIP-P High-Frequency Jitter Tolerance o ±170mV Input Threshold Adjust Range o Clock Holdover Capability Using FrequencySelectable Reference Clock o Serial Loopback Input Availabl.

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Other Datasheets by Maxim Integrated (now Analog Devices)

Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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19-2709; Rev 1; 5/03 KIT ATION EVALU E L B A IL AVA Multirate Clock and Data Recovery with Limiting Amplifier General Description Features o Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps, 1.244Gbps, 622.08Mbps, 155.52Mbps, 1.25Gbps/2.5Gbps (Ethernet) o Reference Clock Not Required for Data Acquisition o Exceeds ANSI, ITU, and Bellcore SONET/SDH Jitter Specifications o 2.7mUIRMS Jitter Generation o 10mVP-P Input Sensitivity Without Threshold Adjust o 0.