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MAX3877 - Clock and Data Retiming ICs

General Description

The MAX3877/MAX3878 are compact, low-power clock recovery and data retiming ICs for 2.488Gbps SONET/ SDH applications.

The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input, which is retimed by the recovered clock.

Key Features

  • o Exceeds ANSI, ITU, and Bellcore SONET/SDH Specifications o Adjustable Input Threshold (±180mV) o 10mVp-p to 1.2Vp-p Differential Input Range o 540mW Power Dissipation (at +3.3V) o Fully Integrated Clock Recovery and Data Retiming o Optional Holdover Capability (Using External Reference Clock) o 0.003UIRMS Clock Jitter Generation o Tolerates >2000 Consecutive Identical Digits o Additional 2.488Gbps Input for Diagnostic Loopback Testing o Differential PECL or CML Data and Clock Outputs o Loss-of.

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📁 Similar Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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19-2062; Rev 0; 5/01 2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust General Description The MAX3877/MAX3878 are compact, low-power clock recovery and data retiming ICs for 2.488Gbps SONET/ SDH applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input, which is retimed by the recovered clock. An additional 2.488Gbps serial input is available for system loopback diagnostic testing, or this input can be connected to a 155MHz reference clock to maintain a valid clock output in the absence of data transitions. The MAX3877/MAX3878 provide vertical threshold and phase-adjust control to optimize system BER in DWDM applications.