SY100E337 Datasheet | Micrel Semiconductor

Micrel, Inc. 3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER SY10E337 SY1S0YE10303E7337 SY100E337 Features s 1500ps max. clock to bus (data transmit) s 1000ps max. clock to Q (data receive) s Extended 100E VEE range of - 4.2V to - 5.5V s 25Ω cutoff bus outputs s 50Ω receiver outputs s Scannable implementation of E336 s Synchronous and asynchronous bus enables s Non-inverting data path s Bus outputs feature internal edge slow-down capacitors s Additional package ground pins s Fully patible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully patible with Motorola MC10E/100E337 s Available in 28-pin PLCC package PIN NAMES Pin A0- A2 B0- B2 S-IN TEN, REN SCAN ABUSDIS SBUSEN SYNCEN CLK BUS0- BUS2 Q0- Q2 VCCO Function Data Inputs A Data Inputs B Serial (Scan) Data Input LOAD/HOLD Controls Scan Control Asynchronous Bus Disable Synchronous Bus Enable Synchronous Enable Control Clock 25Ω Cutoff BUS Outputs Receive Data Outputs (Q2 serves as SCAN_OUT in scan mode) VCC to Output DESCRIPTION The SY10/100E337 are 3-bit registered bus transceivers with scan designed for use in new, high- performance ECL systems. The bus outputs (BUS0- BUS2) are designed to drive a 25Ω bus; the receive outputs (Q0- Q2) are designed for 50Ω. The bus outputs feature a normal logic HIGH level (VOH) and a cutoff LOW level of - 2.0V and the output emitter-follower is “off”, presenting a high impedance to the bus. The bus outputs also feature edge slow-down capacitors. Both drive and receive sides feature the same logic, including a loopback path to hold data. The LOAD/HOLD function is controlled by Transmit Enable (TEN) and Receive Enable (REN) on the transmit and receive sides, respectively, with a HIGH selecting LOAD. The implementation of the E337 Receive Enable differs from that of the E336. A synchronous bus enable (SBUSEN) is provided for normal, non-scan operation. The asynchronous bus disable (ABUSDIS) disables the bus for scan mode. The SYNCEN input...