SY100EL14V Datasheet | Micrel Semiconductor

5V/3.3V 1:5 Clock Distribution General Description The SY100EL14V is a low-skew, 1:5 clock distribution chip designed explicitly for low-skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The EL14V is suitable for operation in systems operating with 3.3V to 5.0V supplies. If a single-ended input is to be used, the VBB output should be connected to the /CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL14V under single-ended input conditions. As a result, this pin can only source/sink up to 0.5m A of current. The EL14V Features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor), the SEL pin will select the differential clock input. The mon enable (/EN) is synchronous, so that the outputs will only be enabled/disable when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock. Therefore, all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and /CLK input will bias around VCC/2. Datasheets and support documentation are available on Micrel’s web site at: .micrel.. Features - 3.3V and 5V power supply options - 70fs RMS typical additive phase jitter - Typical 30ps output-to-output skew - Max. 50ps output-to-output skew - Synchronous enable/disable - Multiplexed clock input - 75kΩ internal input pull-down resistors - Available in 20-pin SOIC package Applications - Processor clock distribution -...