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SY100S834L - Clock Generation Chip

This page provides the datasheet information for the SY100S834L, a member of the SY100S834 Clock Generation Chip family.

Description

The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications.

The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.

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Datasheet preview – SY100S834L

Datasheet Details

Part number SY100S834L
Manufacturer Micrel Semiconductor
File Size 177.49 KB
Description Clock Generation Chip
Datasheet download datasheet SY100S834L Datasheet
Additional preview pages of the SY100S834L datasheet.

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Full PDF Text Transcription

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SY100S834/SY100S834L (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) Clock Generation Chip Precision Edge® General Description The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor.
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