SY100S838 Datasheet | Micrel Semiconductor

Micrel, Inc. NOT REMENDED FOR NEW DESIGNS (÷1, ÷2/3) OR (÷2, ÷4/6) CLOCK GENERATION CHIP Precision Edge® Precision SEYd1g00e S®838 SY1S0Y01S008S38838L SY100S838L Features - 3.3V and 5V power supply options - 50ps output-to-output skew - Synchronous enable/disable - Master Reset for synchronization - Internal 75KΩ input pull-down resistors - Available in 20-pin SOIC package TRUTH TABLE ZZ H NOTES: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition MR L L H Function Divide Hold Q0- 3 Reset Q0- 3 FSEL L L H H DIVSEL L H L H Q0, Q1 OUTPUTS Divide by 2 Divide by 2 Divide by 1 Divide by 1 Q2, Q3 OUTPUTS Divide by 4 Divide by 6 Divide by 2 Divide by 3 PIN NAMES Pin CLK FSEL EN MR VBB Q0, Q1 Q2, Q3 DIVSEL Function Differential Clock Inputs Function Select Input Synchronous Enable Master Reset Reference Output Differential ÷1 or ÷2 Outputs Differential ÷2/3 or ÷4/6 Outputs Frequency Select Input Precision Edge® DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the mon output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S838/L under singleended input conditions. As a result, this pin can only source/sink up to 0.5m A of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S838/L functions as a divide by 2 and by 4/6 clock generation chip. However, if FSEL input is...