SY87702L Datasheet | Micrel Semiconductor

Micrel, Inc. 3.3V 28Mbps-2.5Gbps Any Rate® CLOCK AND DATA RECOVERY Features - 3.3V power supply - plies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, OC-48- , and ATM - patible with FDDI, Gigabit Ethernet, Fibre Channel, 2X Fibre Channel, SMPTE 259 and 292, and proprietary applications - Low power - Clock and data recovery from 28Mbps up to 2.5Gbps NRZ data stream - Selectable reference frequencies via programmable multiplier - Differential PECL and CML high-speed serial outputs - Line receiver input: no external buffering needed - Link fault indication - 100K ECL patible I/O - Available in 64-Pin EP-TQFP package - Product obsolete. Use SY87721L for new designs DESCRIPTION The SY87702L is a plete Clock Recovery and Data retiming integrated circuit for data rates from 28Mbps up to 2.5Gbps NRZ. The device is ideally suited for SONET/SDH/ ATM, Fibre Channel, and Gigabit Ethernet applications, as well as other high-speed data transmission applications. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the ining data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. Onchip clock generation is performed through the use of a frequency multiplier PLL and can be used as a Clock Multiplier Unit (CMU). The integrated CMU can provide this clock signal at the TCLK outputs. Additionally, the TCLK output can be selected to provide a copy of the RCLK frequency. For SONET/SDH applications, the SY87702L includes a Link Fault Detection circuit. This circuit, enabled by the output of an optical module driving the CD input low, causes the recovery PLL of the SY87702L to lock to the reference clock's multiplied frequency under Loss-of-Signal conditions. This low jitter clock is provided at the RCLK outputs and is at the same frequency as that provided at the TCLK output. .. - Meets OC-48...