SY89325V Overview
The SY89325V is a fully differential, CML/PECL/LVPECLto-LVDS translator. It achieves LVDS signaling up to 1.5Gbps and clock rates of 750MHz, depending of the distance and the characteristics of the media and noise coupling sources. LVDS is intended to drive 50Ω impedance transmission line media such as PCB traces, backplanes, or cables.
SY89325V Key Features
- Guaranteed AC performance over temp and voltage
- DC-to >1.5Gbps data rate throughput
- >750MHz clock fMAX
- <50ps within-device skew
- Ultra-low jitter design
- <1psRMS random jitter
- <10psPP deterministic jitter
- <1psRMS cycle-to-cycle jitter
- <10psPP total jitter (clock)
- Accepts CML, PECL, LVPECL inputs