SY89801A Datasheet | Micrel Semiconductor

FEATURES s s s s s 3.3V, - 1.9V power suppies Differential LVPECL clock input Differential HSTL/LVPECL outputs patible with HP PA-8000 microprocessors Low-jitter source for all PA-8000 required timing signals s Available in 44-pin MQUAD package DESCRIPTION Micrel-Synergy's SY89801A PLL based clock generator provides, in a single chip, all the necessary clocks for Hewlett Packard's PA-8000 Microprocessor. Utilizing Micrel-Synergy's advanced PLL technology, the SY89801A accepts a Positive-ECL (PECL) reference clock input at 100MHz-132MHz, and provides precisely aligned, ultra-low-jitter ratios of frequencies necessary for the operation of the processor. In addition, the SY89801A provides the "USYNC" synchronizing signals as required by the PA-8000. The frequency ratios are 1:1, 4:3, 3:2, 5:3 and 2:1. To facilitate direct interfacing to the PA-8000, the SY89801A operates across +3.3 volt and -1.9 volt supplies. The processor clock (PCLK), runway clock (RCLK) , and USYNC outputs are HSTL-patible. Additionally, there is a PECL-patible runway clock output (RCLKLV). The SY89801A requires only a simple external series-RC loop filter. Coupling Micrel-Synergy's advanced PLL technology with our proprietary ASSET bipolar process has produced a Timing Generator IC which meets the stringent requirements of the PA-8000 µP, while setting a new standard for performance and flexibility. PIN CONFIGURATION VEE NC NC REF_CLK REF_CLK VCC 1 44 43 42 41 40 39 38 37 36 VEEA NC NC FILP FILN VCCA NC NC NC NC NC RCLKLV RCLKLV VEE RCLK RCLK 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VEE PCLK1 PCLK1 PCLK2 PCLK2 VCC USYNC USYNC NC NC VCC TOP VIEW MQUAD M44-1 35 34 33 32 31 30 29 VCC NC NC NC FSEL1 FSEL2 VCC NC FSEL0 RST VEE PIN NAMES Pin REF_CLK, REF_CLK FILP, FILN VCCA, VEEA RST FSEL2-0 USYNC, USYNC PCLK1-2, PCLK1-2 RCLK, RCLK RCLKLV, RCLKLV Function Differential Input Ref. Clock Filter Pins (Positive & Negative) Analog VCC, VEE Master Reset...