FEATURES
s 700MHz min. shift frequency s Extended 100E VEE range of –4.2V to –5.5V s 9 bits wide for byte-parity applications s Asynchronous Master Reset s Dual clocks s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E142 s Available in 28-pin PLCC package BLOCK DIAGRAM S-IN D0 1 0 1 D1 0 1 D2 0 1 D3 0 1 D4 0 1 D5 0 1 D6 0 1 D7 0 D8 SEL CLK1 CLK2 MR 1 0 DQ DQ DQ DQ DQ DQ DQ DQ DQ M9999-032006 hbwhelp@micrel.com or (408) 955-1690 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 DESCRIPTION
The SEL (Select) control pin serves to determine the mode of operation, either SHIFT or LOAD. The shift direction is from bit 0 to bit 8. The input data has to meet the set-up time before being clocked into the nine input registers on the rising edge of CLK1 or CLK2. Shifting is also performed on the rising edge of either CLK1 or CLK2. The MR (Master Reset) control signal asynchronously resets all nine registers to a logic LOW when a logic HIGH is applied to MR.
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