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SY89874U - Programmable Clock Divider/Fanout Buffer

General Description

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622 MHz or higher) CML, LVPECL, LVDS, or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock.

Key Features

  • Integrated Programmable Clock Divider and 1:2 Fanout Buffer.
  • Guaranteed AC Performance over Temperature and Voltage: - >2.5 GHz fMAX -.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SY89874U 2.5 GHz, Any Differential In-to-LVPECL, Programmable Clock Divider/Fanout Buffer with Internal Termination Features • Integrated Programmable Clock Divider and 1:2 Fanout Buffer • Guaranteed AC Performance over Temperature and Voltage: - >2.5 GHz fMAX - <250 ps tr/tf - <15 ps Within-Device Skew • Low Jitter Design: - <10 psPP Total Jitter - <1 psRMS Cycle-to-Cycle Jitter • Unique Input Termination and VT Pin for DC-Coupled and AC-Coupled Inputs; CML, PECL, LVDS, and HSTL • TTL/CMOS Inputs for Select and Reset • 100KEP-Compatible LVPECL Outputs • Parallel Programming Capability • Programmable Divider Ratios of 1, 2, 4, 8, and 16 • Low-Voltage Operation: 2.5V or 3.