Datasheet Summary
2.5 GHz, Any Differential In-to-LVPECL, Programmable Clock Divider/Fanout Buffer with Internal Termination
Features
- Integrated Programmable Clock Divider and 1:2 Fanout Buffer
- Guaranteed AC Performance over Temperature and Voltage:
- >2.5 GHz fMAX
- <250 ps tr/tf
- <15 ps Within-Device Skew
- Low Jitter Design:
- <10 psPP Total Jitter
- <1 psRMS Cycle-to-Cycle Jitter
- Unique Input Termination and VT Pin for DC-Coupled and AC-Coupled Inputs; CML, PECL, LVDS, and HSTL
- TTL/CMOS Inputs for Select and Reset
- 100KEP-patible LVPECL Outputs
- Parallel Programming Capability
- Programmable Divider Ratios of 1, 2, 4, 8, and 16
- Low-Voltage Operation: 2.5V or 3.3V
- Output...
