SY89874U Overview
Description
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight passthrough.
Key Features
- Integrated programmable clock divider and 1:2 fanout buffer
- Guaranteed AC performance over temperature and voltage
- >2.5GHz fMAX
- <250ps tr/tf
- <15ps within-device skew
- Low-jitter design
- <10psPP total jitter
- <1psRMS cycle-to-cycle jitter
- Unique input termination and VT pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS, and HSTL
- TTL/CMOS inputs for select and reset
