Datasheet Summary
2.5GHz, Any Differential, In-to-LVPECL, Programmable Clock Divider/Fanout Buffer with Internal Termination
General Description
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight passthrough. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock ponents.
The differential input buffer has a unique internal termination design that allows...
