SY89876L
SY89876L is ANY DIFFERENTIAL IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION manufactured by Micrel Semiconductor.
Micrel, Inc.
3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS ® SY89876L Precision Edge PROGRAMMABLE CLOCK DIVIDER AND SY89876L 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION
Precision Edge®
Features
DESCRIPTION
- Integrated programmable clock divider and 1:2 This low-skew, low-jitter device is capable of accepting a fanout buffer high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency
- Guaranteed AC performance over temperature and using a programmable divider ratio to create a lower speed voltage: version of the input clock. Available divider ratios are 2, 4, 8
- >2.0GHz f MAX and 16, or straight pass-through.
- <190ps tr / tf
- <15ps within device skew The differential input buffer has a unique internal termination design that allows access to the termination
- Low jitter design: network through a VT pin. This feature allows the device to
- <10ps PP total jitter easily interface to different logic standards. A VREF-AC
- <1ps RMS cycle-to-cycle jitter reference is included for AC-coupled applications.
- Unique input termination and VT Pin for DC- and ACThe /RESET input asynchronously resets the divider. In coupled inputs; CML, PECL, LVDS and HSTL the pass-through function (divide by 1) the /RESET
- LVDS-patible outputs synchronously enables or disables the outputs on the next
- TTL/CMOS inputs for select and reset falling edge of IN (rising edge of /IN).
- Parallel programming capability
- Programmable divider ratios of 1, 2, 4, 8 and 16
- Low voltage operation 3.3V
- Output disable function
- - 40°C to 85°C industrial temperature range ..
- Available in 16-pin (3mm × 3mm) MLF® package
TYPICAL PERFORMANCE APPLICATIONS
- SONET/SDH line cards
- Transponders
- High-end, multiprocessor servers
OC-12 to OC-3 Translator/Divider
FUNCTIONAL BLOCK DIAGRAM
S2 (TTL/CMOS)
CML/LVPECL/LVDS 622MHz Clock...
