SY89876L Overview
Description
Integrated programmable clock divider and 1:2 This low-skew, low-jitter device is capable of accepting a fanout buffer high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency - Guaranteed AC performance over temperature and using a programmable divider ratio to create a lower speed voltage: version of the input clock. Available divider ratios are 2, 4, 8 - >2.0GHz fMAX and 16, or straight pass-through.
