SY89876L Description
Integrated programmable clock divider and 1:2 This low-skew, low-jitter device is capable of accepting a fanout buffer high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency Guaranteed AC performance over temperature and using a programmable divider ratio to create a lower speed voltage: version of the input clock. Available divider ratios are 2, 4, 8 >2.0GHz...
SY89876L Key Features
- Integrated programmable clock divider and 1:2 This low-skew, low-jitter device is capable of accepting a fanout buffer h
- Guaranteed AC performance over temperature and using a programmable divider ratio to create a lower speed voltage: versi
- >2.0GHz fMAX and 16, or straight pass-through
- <190ps tr / tf
- <15ps within device skew The differential input buffer has a unique internal termination design that allows access to th
- <10psPP total jitter easily interface to different logic standards. A VREF-AC
- <1psRMS cycle-to-cycle jitter reference is included for AC-coupled
SY89876L Applications
- Unique input termination and VT Pin for DC- and ACThe /RESET input asynchronously resets the divider. In coupled inputs; CML, PECL, LVDS and HSTL the pass-throu