SY89871U Datasheet | Micrel Semiconductor

2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer w/ Internal Termination General Description The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequencylocked lower speed version of the input clock (Bank B). Available divider ratios are 2, 4, 8, and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock ponents. The differential input buffer has a unique internal termination...