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SY89871U - 2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer

General Description

The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequencylocked lower speed vers

Key Features

  • Precision Edge®.
  • Two matched-delay outputs: - Bank A: undivided pass-through (QA) - Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1).
  • Matched delay: all outputs have matched delay, independent of divider setting.
  • Guaranteed AC performance: - >2.5GHz fMAX -.

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Datasheet Details

Part number SY89871U
Manufacturer Micrel Semiconductor
File Size 653.10 KB
Description 2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer
Datasheet download datasheet SY89871U Datasheet

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Full PDF Text Transcription (Reference)

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SY89871U 2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer w/ Internal Termination General Description The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequencylocked lower speed version of the input clock (Bank B). Available divider ratios are 2, 4, 8, and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin.