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SY89875U - IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER

General Description

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock.

Key Features

  • Integrated programmable clock divider and 1:2 fanout buffer.
  • Guaranteed AC performance over temperature and voltage:.
  • > 2.0GHz fMAX.
  • < 200ps tr/tf.
  • < 15ps within device skew.
  • Low jitter design:.
  • < 10psPP total jitter.
  • < 1psRMS cycle-to-cycle jitter.
  • Unique input termination and VT Pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL.
  • LVDS compatible outputs.
  • TTL/CMOS inputs for selec.

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Datasheet Details

Part number SY89875U
Manufacturer Micrel Semiconductor
File Size 218.16 KB
Description IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER
Datasheet download datasheet SY89875U Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Micrel, Inc. 2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS Precision Edge® Precision ESdY8g9e8®75U PROGRAMMABLE CLOCK DIVIDER AND 1:2 SY89875U FANOUT BUFFER W/ INTERNAL TERMINATION FEATURES „ Integrated programmable clock divider and 1:2 fanout buffer „ Guaranteed AC performance over temperature and voltage: • > 2.0GHz fMAX • < 200ps tr/tf • < 15ps within device skew „ Low jitter design: • < 10psPP total jitter • < 1psRMS cycle-to-cycle jitter „ Unique input termination and VT Pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL „ LVDS compatible outputs „ TTL/CMOS inputs for select and reset „ Parallel programming capability „ Programmable divider ratios of 1, 2, 4, 8 and 16 „ Low voltage operation 2.