Datasheet Summary
m o .c U 4 t ™ e 2Mb SYNCBURST e h SRAM S a t a D . Features w w w
NOT REENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM MT58L128L18D, MT58L64L32D, MT58L64L36D
3.3V VDD, 3.3V I/O, Pipelined, Double-Cycle Deselect
- Fast clock and OE# access times
- Single +3.3V +0.3V/-0.165V power supply (VDD)
- Separate +3.3V isolated output buffer supply (VDDQ)
- SNOOZE MODE for reduced-power standby
- mon data inputs and data outputs
- Individual BYTE WRITE control and GLOBAL WRITE
- Three chip enables for simple depth expansion and address pipelining
- Clock-controlled and registered addresses, data I/Os and control signals
- Internally self-timed WRITE cycle
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