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MT46V4M32 - DOUBLE DATA RATE DDR SDRAM

Description

The 128Mb (x32) DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728- bits.

It is internally configured as a quadbank DRAM.

The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation.

Features

  • w w w.
  • VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V.
  • Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data capture.
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle.
  • Reduced output drive option.
  • Differential clock inputs (CK and CK#).
  • Commands entered on each positive CK edge.
  • DQS edge-aligned with data for READs; centeraligned with data for WRITEs.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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m o .c U 4 DOUBLE eDATA RATE et h (DDR) S SDRAM a t a D . FEATURES w w w • VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Reduced output drive option • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask (DM) for masking write data • Programmable burst lengths: 2, 4, 8, or full page • 32ms, 4,096-cycle auto refresh • Auto precharge option • Auto Refresh and Self Refresh Modes • 2.
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