MT47H256M4 Overview
DDR2 SDRAM MT47H256M4 32 Meg x 4 x 8 banks MT47H128M8 16 Meg x 8 x 8 banks MT47H64M16 8 Meg x 16 x 8 banks 1Gb: x4, x8, x16 DDR2.
MT47H256M4 Key Features
- VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
- JEDEC-standard 1.8V I/O (SSTL_18-patible)
- Differential data strobe (DQS, DQS#) option
- 4n-bit prefetch architecture
- Duplicate output strobe (RDQS) option for x8
- DLL to align DQ and DQS transitions with CK
- 8 internal banks for concurrent operation
- Programmable CAS latency (CL)
- Posted CAS additive latency (AL)
- WRITE latency = READ latency