MT48LC32M4A2 Overview
SDR SDRAM MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks 128Mb: x4, x8, x16.
MT48LC32M4A2 Key Features
- PC100- and PC133-pliant
- Fully synchronous; all signals registered on positive
- Internal, pipelined operation; column address can
- Internal banks for hiding row access/precharge
- Programmable burst lengths (BL): 1, 2, 4, 8, or full
- Auto precharge, includes concurrent auto precharge
- Self refresh modes: Standard and low power
- Auto Refresh
- 64ms, 4096-cycle refresh (mercial and industrial)
- 16ms, 4096-cycle refresh (automotive)