MT48LC128M4A2 Datasheet PDF - Micron Technology (MT48LCxxMxxA2) SYNCHRONOUS DRAM Specs

MT48LC128M4A2 - (MT48LCxxMxxA2) SYNCHRONOUS DRAM

This page provides the datasheet information for the MT48LC128M4A2, a member of the MT48LC32M16A2 (MT48LCxxMxxA2) SYNCHRONOUS DRAM family.

Datasheet Summary

Description

The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.

It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).

Features

PC100- and PC133-compliant.
Fully synchronous; all signals registered on positive edge of system clock.
Internal pipelined operation; column address can be changed every clock cycle.
Internal banks for hiding row access/precharge.
Programmable burst lengths: 1, 2, 4, 8, or full page.
Auto Precharge, includes.

Datasheet Details

Part number	MT48LC128M4A2
Manufacturer	Micron Technology
File Size	2.23 MB
Description	(MT48LCxxMxxA2) SYNCHRONOUS DRAM
Datasheet	MT48LC128M4A2 Datasheet
Additional preview pages of the MT48LC128M4A2 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com ADVANCE‡ 512Mb: x4, x8, x16 SDRAM SYNCHRONOUS DRAM FEATURES • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Mode • 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply MT48LC128M4A2 – 32 Meg x 4 x 4 banks MT48LC64M8A2 – 16 Meg x 8 x 4 banks MT48LC32M16A2 – 8 Meg x 16 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.

Published: Sep 16, 2006 |