MT48LC128M4A2 Overview
x4, x8, x16 SDRAM SYNCHRONOUS DRAM.
MT48LC128M4A2 Key Features
- PC100- and PC133-pliant
- Fully synchronous; all signals registered on positive edge of system clock
- Internal pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Programmable burst lengths: 1, 2, 4, 8, or full page
- Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
- Self Refresh Mode
- 64ms, 8,192-cycle refresh
- LVTTL-patible inputs and outputs
- Single +3.3V ±0.3V power supply