MT48LC16M16LF Datasheet | Micron Technology

Features - Fully synchronous; all signals registered on positive edge of system clock - Internal pipelined operation; column address can be changed every clock cycle - Internal banks for hiding row access/precharge - Programmable burst lengths: 1, 2, 4, 8, or full page - Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes - Self Refresh Mode - 64ms, 8,192-cycle refresh - LVTTL-patible inputs and outputs - Low voltage power supply - Temperature pensated Self Refresh (TCSR) Option Marking - VDD/VDDQ LC 3.3V/3.3V G 3.0V/3.0V V 2.5V/2.5V-1.8V - Configurations 16M16 16 Meg x 16 (4 Meg x 16 x 4 banks) - Plastic Packages - OCPL TG 54-pin TSOP (400 mil)1 P 54-pin TSOP (400 mil) Lead-Free1 FG 54-ball VFBGA (8mm x 14mm)2 BG 54-ball VFBGA (8mm x 14mm) Lead-Free2 F8 54-ball VFBGA (11mm x 8mm)2 B8 54-ball VFBGA (11mm x 8mm) Lead-Free2 - Timing (Cycle Time) -75 7.5ns @ CL = 3 (133MHz) -8 8.0ns @ CL = 3 (125 MHz) -10 9.6ns @ CL = 3 (104 MHz) - Self Refresh None Standard - Operating Temperature None mercial (0o C to + 70o C) XT Extended (-25o C to + 75o C) IT Industrial (-40o C to + 85o C) NOTE: 1. Contact Factory for availability. 2. Due to space limitations, FBGA-packaged ponents have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on the Micron web site, .micron./decoder. MT48LC16M16LF, MT48G16M16LF, MT48V16M16LF 4 MEG X 16 X 4 BANKS Figure 1: Ball Assignment (Top View) 54-Ball VFBGA 1 A B C D E F G H J 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 VSSQ VDDQ DQ0 DQ14 VDDQ VSSQ DQ2 DQ1...