MT48LC16M16LFBG Datasheet PDF - Micron Technology 256M x 16 Mobile SDRAM Specs

MT48LC16M16LFBG - 256M x 16 Mobile SDRAM

This page provides the datasheet information for the MT48LC16M16LFBG, a member of the MT48LC16M16LFFG 256M x 16 Mobile SDRAM family.

Datasheet Summary

Description

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.

It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).

Features

Temperature Compensated Self Refresh (TCSR).
Fully synchronous; all signals registered on positive edge of system clock.
Internal pipelined operation; column address can be changed every clock cycle.
Internal banks for hiding row access/precharge.
Programmable burst lengths: 1, 2, 4, 8, or full page.
Auto Precharge, includes.

Datasheet Details

Part number	MT48LC16M16LFBG
Manufacturer	Micron Technology
File Size	1.65 MB
Description	256M x 16 Mobile SDRAM
Datasheet	MT48LC16M16LFBG Datasheet
Additional preview pages of the MT48LC16M16LFBG datasheet.

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Full PDF Text Transcription

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PRELIMINARY‡ 256Mb: x16 MOBILE SDRAM MOBILE SDRAM FEATURES • Temperature Compensated Self Refresh (TCSR) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes • Self Refresh Mode • 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Low voltage power supply • Deep Power Down • Partial Array Self Refresh power-saving mode MT48LC16LFFG, MT48LC16M16LFBG, MT48V16MLFFG, MT48V16M16LFBG, MT48H16M16LFFG, MT48H16M16LFBG 4 Meg x 16 x 4 banks For the latest data sheet revisions, please refer to the Micron

Published: Apr 8, 2006 |