MT4LC8M8B6 Overview
The 8 Meg x 8 DRAMs are high-speed CMOS, dynamic random-access memory devices containing 67,108,864 bits organized in a x8 configuration. The 8 Meg x 8 DRAMs are functionally organized as 8,388,608 locations containing eight bits each. During READ or WRITE cycles, each location is uniquely addressed via the address bits.
MT4LC8M8B6 Key Features
- Single +3.3V ±0.3V power supply
- Industry-standard x8 pinout, timing, functions, and packages
- High-performance CMOS silicon-gate process
- All inputs, outputs and clocks are LVTTLpatible
- FAST PAGE MODE (FPM) access
- 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms
- Optional self refresh (S) for low-power data retention
- Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows
- Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil)
- Timing 50ns access 60ns access