MT4LC8M8C2 Datasheet PDF (DRAM) | Download Micron Technology MT4LC8M8C2

MT4LC8M8C2 - DRAM

This page provides the datasheet information for the MT4LC8M8C2, a member of the MT4LC8M8P4 DRAM family.

Description

The 8 Meg x 8 DRAM is a high-speed CMOS, dynamic random-access memory devices containing 67,108,864 bits and designed to operate from 3V to 3.6V.

The MT4LC8M8C2 and MT4LC8M8P4 are functionally organized as 8,388,608 locations containing eight bits each.

Features

Single +3.3V ±0.3V power supply.
Industry-standard x8 pinout, timing, functions, and packages.
12 row, 11 column addresses (C2) or 13 row, 10 column addresses (P4).
High-performance CMOS silicon-gate process.
All inputs, outputs and clocks are LVTTLcompatible.
Extended Data-Out (EDO) PAGE MODE access.
4,096-cycle CAS#-BEFORE-RAS# (CBR).

Datasheet Details

Part number	MT4LC8M8C2
Manufacturer	Micron Technology
File Size	397.75 KB
Description	DRAM
Datasheet	MT4LC8M8C2 Datasheet
Additional preview pages of the MT4LC8M8C2 datasheet.

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Full PDF Text Transcription

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8 MEG x 8 EDO DRAM DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x8 pinout, timing, functions, and packages • 12 row, 11 column addresses (C2) or 13 row, 10 column addresses (P4) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTLcompatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention MT4LC8M8P4, MT4LC8M8C2 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.

Published: Jan 16, 2006 |