Micron Technology MT4LC8M8C2
The MT4LC8M8C2 and MT4LC8M8P4 are functionally organized as 8,388,608 locations containing eight bits each. The 8,388,608 memory locations are arranged in 4,096 rows by 2,048 columns on the C2 version and 8,192 rows by 1,024 columns on the P4 version.| Part No. | MT4LC8M8C2 |
|---|---|
| Datasheet | MT4LC8M8C2 Download |
| Manufacturer |  Micron Technology |
| Description | DRAM |
| Buy | Stock & Price |
FEATURES
● Single +3.3V ±0.3V power supply● Industry-standard x8 pinout, timing, functions, and packages
● 12 row, 11 column addresses (C2) or 13 row, 10 column addresses (P4)
● High-performance CMOS silicon-gate process
● All inputs, outputs and clocks are LVTTLcompatible
● Extended Data-Out (EDO) PAGE MODE access
● 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms
● Optional self refresh (S) for low-power data retention MT4LC8M8P4, MT4LC8M8C2 For the latest data sheet, please refer to the Micron Web site: PIN ASSIGNMENT (Top View) 32-Pin SOJ VCC DQ0 DQ1 DQ2 DQ3 NC VCC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 32-Pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ7 DQ6 DQ5 DQ4 VSS CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 VSS OPTIONS
● Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows
● Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil)
● Timing 50ns access 60ns access
● Refresh Rates Standard Refresh (64ms period) Self R...
