ZL30253 Datasheet | Microsemi

Register Map: Section 6.2 Features - Input Clocks - Three inputs: two differential/CMOS, one CMOS - Any input frequency from 1k Hz to 1250MHz (1k Hz to 300MHz for CMOS) - Inputs continually monitored for activity and frequency accuracy - Automatic or manual reference switching - Low-Bandwidth DPLL - Programmable bandwidth, 14Hz to 500Hz - Attenuates jitter up to several UI - Freerun or digital hold on loss of all inputs - Digitally controlled phase adjustment - Low-Jitter Fractional-N APLL and 3 Outputs - Any output frequency from <1Hz to 1035MHz - High-resolution fractional frequency conversion with 0ppm error - Easy-to-configure, encapsulated design requires no external VCXO or loop filter ponents - Each output has independent dividers - Output jitter is typically 0.16 to 0.28ps RMS (12k Hz-20MHz integration band) - Outputs are CML or 2x CMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL - In 2x CMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz) ZL30252, ZL30253 3-Input, 3-Output Any-to-Any Clock Multiplier and Jitter Attenuator ICs Data Sheet January 2018 Ordering Information ZL30252LDG1 ZL30252LDF1 ZL30253LDG1 ZL30253LDF1 32 Pin QFN 32 Pin QFN 32 Pin QFN 32 Pin QFN Trays Tape and Reel Trays Tape and Reel Matte Tin Package size: 5 x 5 mm -40C to...