Datasheet Summary
®
Multiple Output Trunk PLL Advance Information
Features
- Provides T1 and E1 clocks, and ST-BUS/GCI framing signals locked to an input reference of either 8 kHz (frame pulse), 1.544 MHz (T1), or 2.048 MHz (E1) Meets AT & T TR62411 and ETSI ETS 300 011 specifications for a 1.544 MHz (T1), or 2.048 MHz (E1) input reference Typical unfiltered intrinsic output jitter is 0.013 UI peak-to-peak Jitter attenuation of 15 dB @ 10 Hz, 34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz Low power CMOS technology
ISSUE 1
May 1995
Ordering Information MT9041AP 28 Pin PLCC -40 °C to +85 °C
- Description
The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization...